Yokohama, Japan

Hura Harpreet Singh

This inventor holds 1 USPTO granted patent. Top assignee: Opnext Japan, Inc.. Active years: 2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hura Harpreet Singh. Retrieved from https://idiyas.com/inventor/hura-harpreet-singh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2008

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1 patent (USPTO):Explore Patents

Title: Hura Harpreet Singh: Semiconductor Polishing Invention.

Introduction

Hura Harpreet Singh is an inventor associated with Yokohama, Japan. Her work includes an invention addressing damage to semiconductor substrates during polishing.

Latest Patents

Singh is credited with 1 patent: “Polishing Method for Semiconductor Substrate, and Polishing Jig Used Therein.” The invention describes a fixing jig with one or more grooves on the substrate-facing surface, sized approximately to match the semiconductor substrate’s diameter. The jig is intended to help suppress outer-surface damage and cracking that can occur when a thinned, weakened wafer is polished.

Career Highlights

Singh is associated with Opnext Japan, Inc. Her patent focuses on a practical challenge in semiconductor manufacturing: protecting wafers whose strength has been reduced through polishing.

Collaborations

Kenji Uchida and Ryu Washino are identified as Singh’s coworkers.

Conclusion

Hura Harpreet Singh’s semiconductor polishing invention presents a jig-based approach to reducing substrate damage and cracking during wafer processing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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