New Taipei, Taiwan

Hsueh Han Lu

This inventor holds 1 USPTO granted patent. Top assignee: Nan Ya Technology Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsueh Han Lu. Retrieved from https://idiyas.com/inventor/hsueh-han-lu-t07953te

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Hsueh Han Lu: Innovator in Asymmetric Pad Structures

Introduction

Hsueh Han Lu is a notable inventor based in New Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly with his innovative designs that enhance the efficiency of wafer processing.

Latest Patents

Hsueh Han Lu holds a patent for an invention titled "Asymmetric pads structure and test element group module." This invention provides an asymmetric pads structure used at a scribe line of a wafer. It comprises a test element device that is electrically connected to a first pad and a second pad separately. The first spacing between the second pad and the test element device is sufficient to accommodate the second pad of another asymmetric pads structure. This design allows two neighboring asymmetric pads structures to cross each other, forming a cross configuration. He has 1 patent to his name.

Career Highlights

Hsueh Han Lu is currently employed at Nan Ya Technology Corporation, where he continues to develop innovative solutions in semiconductor technology. His work has been instrumental in advancing the capabilities of wafer processing techniques.

Collaborations

Hsueh Han Lu collaborates with talented individuals in his field, including coworkers Chiang-lin Shih and Meng-Zhen Li. Their combined expertise contributes to the success of their projects and innovations.

Conclusion

Hsueh Han Lu is a prominent figure in the realm of semiconductor innovations, with a focus on asymmetric pad structures that enhance wafer processing. His contributions are paving the way for advancements in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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