Sunnyvale, CA, United States of America

Hsiao Yu Chang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Ndtm US LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsiao Yu Chang. Retrieved from https://idiyas.com/inventor/hsiao-yu-chang-ikd97ff2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Hsiao Yu Chang: Innovator in NAND Memory Technology

Introduction

Hsiao Yu Chang is a notable inventor based in Sunnyvale, CA (US). He has made significant contributions to the field of memory technology, particularly in NAND memory arrays. His innovative work focuses on enhancing power efficiency in memory systems.

Latest Patents

Hsiao Yu Chang holds a patent titled "Power efficient array discharge for program boosting." This patent describes systems, apparatuses, and methods that issue a program pulse to a selected subblock of a NAND memory array. It also includes a pulse recovery phase after the program pulse and the shutdown of unselected subblocks during this recovery phase. This technology aims to improve the efficiency and performance of NAND memory systems.

Career Highlights

Hsiao Yu Chang is currently employed at Intel NDTM US LLC, where he continues to develop cutting-edge technologies in memory systems. His work at Intel has positioned him as a key player in the advancement of NAND memory technology.

Collaborations

Hsiao collaborates with Tarek Ameen, a fellow innovator in the field. Their combined expertise contributes to the development of advanced memory solutions.

Conclusion

Hsiao Yu Chang's contributions to NAND memory technology through his innovative patent and work at Intel highlight his role as a significant inventor in the field. His efforts continue to push the boundaries of memory efficiency and performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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