Hsiang-Chieh Liao

Title: Hsiang-Chieh Liao: Innovator in Integrated Circuit Design

Introduction

Hsiang-Chieh Liao is a notable inventor based in San Ramon, CA. He has made significant contributions to the field of integrated circuit design. His innovative approach to fault analysis in circuit design has garnered attention in the industry.

Latest Patents

Hsiang-Chieh Liao holds a patent for "In-graph causality ranking for faults in the design of integrated circuits." This patent utilizes a graph to assist users in analyzing the causes of faults. The graph represents signal flow through the design of an integrated circuit, incorporating elements such as nodes and edges. Nodes represent cells and nets in the circuit design, while edges illustrate the signal flow between them. A propagation model is constructed to analyze the propagation of faults through these graph elements. This model allows for the backward modeling of a known fault, resulting in a causality ranking of the graph elements as potential causes of the fault. The information regarding this causality ranking is displayed in a user interface that showcases the integrated circuit design.

Career Highlights

Hsiang-Chieh Liao is currently employed at Synopsys, Inc., where he continues to innovate in the field of integrated circuits. His work has had a profound impact on the design and analysis of complex electronic systems.

Collaborations

He collaborates with talented individuals such as Xiang Gao and Chia-Chih Yen, contributing to advancements in integrated circuit technology.

Conclusion

Hsiang-Chieh Liao's contributions to integrated circuit design through his innovative patent demonstrate his expertise and commitment to advancing technology. His work continues to influence the field and inspire future innovations.