The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Feb. 10, 2022
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Xiang Gao, San Jose, CA (US);

Hsiang-Chieh Liao, San Ramon, CA (US);

Chia-Chih Yen, Taipei, TW;

Sashikala Venkata Obilisetty, Los Altos, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/31 (2020.01); G06F 30/3312 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/31 (2020.01); G06F 30/3312 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01);
Abstract

In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the propagation of faults through the graph elements. Propagation of a known fault backward through the graph is modeled using the propagation model. This results in a causality ranking of the graph elements as possible causes of the known fault. Information indicative of the causality ranking is displayed in a user interface that shows the design of the integrated circuit.


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