Hoong Chin Ng

Title: Hoong Chin Ng and Memory-System Timing Innovation.

Introduction

Hoong Chin Ng is an inventor based in Bayan Lepas, Malaysia, and is associated with SkyeChip Berhad. His patent work addresses clock timing in memory systems, where precise synchronization can support reliable communication between system components.

Latest Patents

Ng is credited with 1 patent: “Digital Delay Line of a Memory System and Method of Adjusting Timing of Clocks Using Thereof.” The invention describes a digital delay line with coarse and fine delay stages. The coarse stage receives a high-speed input clock, divides its frequency to produce an interface output clock, and adjusts the divided clock’s timing. It uses a dual-edge-triggered flip-flop to generate a shifted divided clock and a clock multiplexer to bypass the input clock when shifting is unnecessary. The fine stage provides smaller delay increments and transmits the interface output clock to transceivers. The patent also describes a method for adjusting clock timing in a memory system using this arrangement.

Career Highlights

Ng’s listed patent reflects work on memory-system clock management, combining frequency division with adjustable coarse and fine delays. He is associated with SkyeChip Berhad, a company working in the semiconductor field.

Collaborations

How Hwan Wong, identified as a woman, is listed as Ng’s coworker. The available information does not specify her role in the patent or describe any direct collaboration between them.

Conclusion

Hoong Chin Ng’s patent focuses on a configurable digital delay line for adjusting clock timing in memory systems, highlighting his contribution to semiconductor and memory-interface innovation.