Tokyo, Japan

Hiroko Yazawa

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Toppan Holdings Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroko Yazawa. Retrieved from https://idiyas.com/inventor/hiroko-yazawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Hiroko Yazawa’s Microfluidic Chip Invention.

Introduction

Hiroko Yazawa is an inventor associated with Toppan Holdings Inc. in Tokyo, Japan. Her patent work focuses on microfluidic chip design and production.

Latest Patents

Yazawa is credited with 1 patent, titled “Microfluidic Chips and Methods of Producing Microfluidic Chips.” The invention describes a chip with a fluidic channel formed between a cover layer and a substrate, using partition layers to define the channel. A curved portion of a partition layer creates a bubble-trapping region with the cover layer, helping capture air bubbles within the channel.

Career Highlights

The patent reflects Yazawa’s work on microfluidic structures and methods for producing chips. Its bubble-trapping design addresses air management within fluidic channels.

Collaborations

Yazawa’s patent is associated with Toppan Holdings Inc., a company connected to her innovation in microfluidic chip technology.

Conclusion

Hiroko Yazawa’s patented design uses a purpose-built region to trap bubbles in microfluidic channels, highlighting her contribution to chip engineering.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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