Hideki Ishida

Title: Innovations by Hideki Ishida in Integrated Circuit Yield Estimation

Introduction

Hideki Ishida is a notable inventor based in Toyama, Japan. He has made significant contributions to the field of integrated circuits, particularly in the estimation of yield for these devices. His innovative approach has led to the development of a unique method that enhances the accuracy of yield predictions.

Latest Patents

Hideki Ishida holds a patent for a "Method for estimating yield of integrated circuit device." This patent involves a comprehensive process where necessary information such as chip area A, number of elements, and defect density D is inputted to calculate element density TD and mean element density TDM. The method utilizes Stapper's equation to establish the relationship between yield, defect density, and chip area. By determining the functional relation g (TD/TDM) from various integrated circuit devices, Ishida calculates a correction factor K, which is then used to predict the expected yield Y.

Career Highlights

Ishida is associated with Matsushita Electric Industrial Co., Ltd., a company renowned for its advancements in electronics and technology. His work has been instrumental in improving the efficiency and reliability of integrated circuits, making a lasting impact on the industry.

Collaborations

One of his notable collaborators is Takao Kuroda, with whom he has worked closely on various projects related to integrated circuits. Their combined expertise has contributed to the development of innovative solutions in the field.

Conclusion

Hideki Ishida's contributions to the estimation of yield in integrated circuits exemplify the importance of innovation in technology. His patent and collaborative efforts continue to influence advancements in the electronics industry.