Suwon-si, South Korea

Heejae Nam

This inventor holds 2 USPTO granted patents. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Heejae Nam. Retrieved from https://idiyas.com/inventor/heejae-nam-2w7v56h9

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0


Company Filing History:


Years Active: 2026

Loading Chart...
2 patents (USPTO):Explore Patents

Title: Heejae Nam’s Semiconductor Packaging and Wafer-Dicing Innovations.

Introduction

Heejae Nam is an inventor based in Suwon-si, South Korea, whose patent work focuses on semiconductor manufacturing and packaging. His listed portfolio includes 2 patents, and he is associated with Samsung Electronics Ltd.

Latest Patents

Nam’s listed inventions address wafer dicing and semiconductor package construction.

“Wafer dicing method forming internal cracks by laser beam and method of manufacturing semiconductor device by using the same” describes a process for separating semiconductor devices from a wafer. The method forms grooves in the wafer’s scribe lanes, uses a laser beam along the grooves to create internal cracks, and separates the devices along those cracks.

“Semiconductor package and method of manufacturing the semiconductor package” describes a package with stacked groups of semiconductor chips. Bonding wires connect the chip pads to substrate pads positioned at different heights, providing electrical connections for the stacked chips.

Career Highlights

Nam’s listed patent work concerns two important stages of semiconductor production: separating devices from a wafer and assembling chips into a package. These inventions describe manufacturing approaches intended to support device separation and electrical interconnection in semiconductor packages.

Collaborations

Nam is associated with Samsung Electronics Ltd. His listed coworker is Junggeun Shin.

Conclusion

Heejae Nam’s patent portfolio reflects work on wafer dicing and stacked semiconductor packaging, linking manufacturing processes with the assembly of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…