The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

May. 19, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Heejae Nam, Suwon-si, KR;

Junyun Kweon, Suwon-si, KR;

Wooju Kim, Suwon-si, KR;

Junggeun Shin, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 74/10 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 72/884 (2026.01); H10W 74/111 (2026.01); H10W 90/24 (2026.01); H10W 90/701 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package including a package substrate having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads along a side portion thereof and second substrate pads outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads, a first group of semiconductor chips sequentially stacked on the upper surface of the package substrate, and including at least one semiconductor chip, a second group of semiconductor chips sequentially stacked on the first group of semiconductor chips and including at least one semiconductor chip, first bonding wires electrically connecting chip pads of the first group of semiconductor chips to the first substrate pads, respectively, and second bonding wires electrically connecting chips pads of the second group of semiconductor chips to the second substrate pads, respectively may be provided.


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