Santa Clara, CA, United States of America

Haritez Narisetty

This inventor holds 1 USPTO granted patent and 4 published patent applications. Top assignee: Globalfoundries Inc.. Active years: 2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Haritez Narisetty. Retrieved from https://idiyas.com/inventor/haritez-narisetty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2017

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Haritez Narisetty: Innovator in Semiconductor Technology

Introduction

Haritez Narisetty is a notable inventor based in Santa Clara, California. He has made significant contributions to the field of semiconductor technology, particularly in reducing antenna effects in Silicon-on-Insulator (SOI) devices. His innovative work has led to the development of a patent that addresses critical challenges in semiconductor design.

Latest Patents

Narisetty holds a patent for a semiconductor device that comprises a power line and a Silicon-on-Insulator substrate. This device includes a semiconductor layer and a semiconductor bulk substrate featuring a first doped region. The invention also encompasses a first transistor device formed in and above the SOI substrate, which includes a first gate dielectric and a first gate electrode. Additionally, the device features a first diode electrically connected to the first gate electrode and a second diode connected to the first diode and the power line. Notably, the first and second diodes are partially formed in the first doped region. This patent exemplifies Narisetty's commitment to advancing semiconductor technology.

Career Highlights

Haritez Narisetty is currently employed at GlobalFoundries Inc., a leading semiconductor manufacturer. His work at the company has allowed him to collaborate with other talented professionals in the field. Narisetty's expertise in semiconductor devices has positioned him as a valuable asset to his team and the industry.

Collaborations

Some of Narisetty's coworkers include Ingolf Lorenz and Stefan G Block. Their collaboration fosters an environment of innovation and creativity, contributing to the advancement of semiconductor technologies.

Conclusion

Haritez Narisetty is a distinguished inventor whose work in semiconductor technology has led to significant advancements in the field. His patent for reducing antenna effects in SOI devices showcases his innovative spirit and dedication to improving semiconductor design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…