The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Feb. 22, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ingolf Lorenz, Dresden, DE;

Stefan Block, Munich, DE;

Ulrich Hensel, Dresden, DE;

Jürgen Faul, Dresden, DE;

Michael Zier, Dresden, DE;

Haritez Narisetty, Santa Clara, CA (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/62 (2006.01); H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 27/0255 (2013.01); H01L 27/1203 (2013.01); H01L 29/66121 (2013.01); H01L 29/66568 (2013.01);
Abstract

It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.


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