This inventor holds 1 USPTO granted patent. Top assignee: Globalfoundries Inc.. Active years: 2018.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2018
Title: Hariharasudhan Kathiresan: Advancing Overlay Sampling in Semiconductor Manufacturing.
Introduction
Hariharasudhan Kathiresan is an inventor based in Dresden, Germany, and is associated with GlobalFoundries Inc. His patent work addresses overlay measurement, an important part of monitoring alignment in semiconductor wafer manufacturing.
Latest Patents
Kathiresan is named on 1 patent, titled “Overlay Sampling Reduction.” The invention describes a method and apparatus for reducing the number of overlay measurements while predicting overlay values in unmeasured wafer regions. It involves measuring selected field corners, separating measured errors into interfield and intrafield components, and using averages from a virtual stack of fields to estimate values at unmeasured corners.
Career Highlights
The patent reflects Kathiresan’s contribution to semiconductor process measurement and wafer-overlay analysis. By estimating unmeasured overlay values from a reduced set of measurements, the disclosed approach aims to make sampling more efficient while retaining information about correctable and non-correctable errors.
Collaborations
Kathiresan is associated with GlobalFoundries Inc. His coworker, Eric Cotte, is also identified in the provided information.
Conclusion
Hariharasudhan Kathiresan’s patent focuses on reducing overlay sampling while predicting measurements across wafer regions, highlighting his work in semiconductor manufacturing innovation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile