Kaohsiung, Taiwan

Han-Lin Hsu

This inventor holds 1 USPTO granted patent. Top assignee: United Microelectronics Corp.. Active years: 2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Han-Lin Hsu. Retrieved from https://idiyas.com/inventor/han-lin-hsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2017

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1 patent (USPTO):Explore Patents

Title: The Innovations of Han-Lin Hsu

Introduction

Han-Lin Hsu is a prominent inventor based in Kaohsiung, Taiwan. He is known for his contributions to the field of semiconductor technology, particularly in the development of methods for enhancing the performance of MOS transistors. His innovative approach has led to significant advancements in the industry.

Latest Patents

Han-Lin Hsu holds a patent for a "Method of forming gate dielectric layer for MOS transistor." This method involves several steps, including the formation of a gate dielectric layer on a substrate, followed by a nitridation process. Additionally, a multi-step post-nitridation annealing process is performed, which includes two oxygen-containing annealing steps at different temperatures. This innovative technique aims to improve the efficiency and reliability of MOS transistors.

Career Highlights

Han-Lin Hsu is currently employed at United Microelectronics Corporation, a leading company in the semiconductor industry. His work at this organization has allowed him to collaborate with other talented professionals and contribute to groundbreaking research and development projects.

Collaborations

Some of Han-Lin Hsu's notable coworkers include Po-Lun Cheng and Chun-Liang Chen. Their collaborative efforts have further enhanced the innovative capabilities of their team, leading to advancements in semiconductor technologies.

Conclusion

Han-Lin Hsu's contributions to the field of semiconductor technology exemplify the impact of innovative thinking in the industry. His patent for the method of forming a gate dielectric layer for MOS transistors showcases his commitment to advancing technology and improving device performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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