Taipei, Taiwan

Han-Chang Pan

This inventor holds 1 USPTO granted patent. Top assignee: Everlight Electronics Co., Ltd.. Active years: 2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Han-Chang Pan. Retrieved from https://idiyas.com/inventor/han-chang-pan-fjri9fta

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 8.0

ph-index = 1


Company Filing History:


Years Active: 2020

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1 patent (USPTO):Explore Patents

Title: Han-Chang Pan: Innovator in Semiconductor Packaging

Introduction

Han-Chang Pan is a notable inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor packaging, showcasing his expertise through innovative designs and structures.

Latest Patents

Han-Chang Pan holds a patent for a semiconductor package structure. This package structure includes a first substrate, a second substrate on which the first substrate is disposed, and a semiconductor chip that is placed on the first substrate. The design features two notches or solder receiving portions on the substrates, allowing the package structure to protrude less on the surface of the printed circuit board (PCB). This innovation ensures that the solders on the PCB remain stable and are not shifted by the package structure.

Career Highlights

Han-Chang Pan is currently employed at Everlight Electronics Co., Ltd. His work at this company has allowed him to further develop his skills and contribute to advancements in semiconductor technology.

Collaborations

Some of his coworkers include Chih-Ming Ho and Chun-Chih Liang, who collaborate with him on various projects within the company.

Conclusion

Han-Chang Pan's contributions to semiconductor packaging demonstrate his innovative spirit and commitment to advancing technology in this field. His patent reflects a significant step forward in improving the functionality and reliability of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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