Los Altos, CA, United States of America

Geraud J M Dubois

This inventor holds 2 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 2014-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Geraud J M Dubois. Retrieved from https://idiyas.com/inventor/geraud-j-m-dubois

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.4

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2014-2019

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2 patents (USPTO):Explore Patents

Title: Geraud J M Dubois: Innovator in Surface Modification and Semiconductor Technology

Introduction

Geraud J M Dubois is a notable inventor based in Los Altos, California. He has made significant contributions to the fields of surface modification and semiconductor technology. With a total of 2 patents to his name, Dubois continues to push the boundaries of innovation.

Latest Patents

One of Dubois' latest patents is titled "Surface modification by polymer anchoring on porous substrates." This invention discloses a method for mechanically anchoring polymers on the surface of a porous substrate by trapping polymer chains within the pores of the substrate under capillary forces. The method allows for surface modification of the porous substrate by anchoring one end of the polymer chains within the pores while allowing one or more other ends to dangle from the surface. This unique approach modifies the surface of a material without the need for chemical reactions or precursor-substrate interactions.

Another significant patent is "Semiconductor interconnect structure having enhanced performance and reliability." This invention outlines an interconnect structure and method for fabricating it, which enhances performance and reliability by minimizing oxygen intrusion into a seed layer and an electroplated copper layer. The process involves forming at least one opening in a dielectric layer, creating a sacrificial oxidation layer to minimize oxygen intrusion, and subsequently forming a barrier metal layer, seed layer, and electroplated copper layer. The result is a planarized surface that improves the overall reliability of semiconductor interconnects.

Career Highlights

Geraud J M Dubois is currently employed at International Business Machines Corporation (IBM), where he applies his expertise in innovative technologies. His work has contributed to advancements in both surface modification techniques and semiconductor structures.

Collaborations

Throughout his career, Dubois has collaborated with notable colleagues, including Cyril Cabral, Jr. and Daniel C Edelstein. These collaborations have further enriched his contributions to the field of technology.

Conclusion

Geraud J M Dubois is a distinguished inventor whose work in surface modification and semiconductor technology has led to significant advancements. His innovative patents reflect his commitment to enhancing material properties and improving semiconductor performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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