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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8841770 B1

PDFFull Text
Date of Patent:
Sep. 23, 2014

Filed:

Nov. 14, 2013

Semiconductor interconnect structure having enhanced performance and reliability

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Cyril Cabral, Jr., Mahopac, NY (US);

Geraud J. M. Dubois, Los Altos, CA (US);

Daniel C. Edelstein, White Plains, NY (US);

Takeshi Nogami, Schenectady, NY (US);

Daniel P. Sanders, San Jose, CA (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorney:

Nicholas L. Cadmus

Primary Examiner:

Jasmine Clark

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/53266 (2013.01); H01L 21/76873 (2013.01); H01L 21/76846 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 21/76849 (2013.01); H01L 21/76831 (2013.01); H01L 21/76867 (2013.01);
Abstract

An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Find Patent Forward Citations

Cabral, Jr., Cyril. (2014). Semiconductor interconnect structure having enhanced performance and reliability (U.S. Patent No. 8841770). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8841770

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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