Delft, Netherlands

Gerasimos S Vlachogiannakis

This inventor holds 2 USPTO granted patents. Top assignee: Short Circuit Technologies LLC. Active years: 2016-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gerasimos S Vlachogiannakis. Retrieved from https://idiyas.com/inventor/gerasimos-s-vlachogiannakis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 50.0

Average Co-Inventor Count = 3.0

ph-index = 2

Forward Citations = 21(Granted Patents)


Company Filing History:


Years Active: 2016-2017

Loading Chart...
2 patents (USPTO):Explore Patents

Title: Gerasimos S Vlachogiannakis: Innovating Power Reduction in Frequency Synthesizers

Introduction:

In the world of technological advancements, inventors and innovators play a crucial role in shaping the future. Gerasimos S Vlachogiannakis, based in Delft, Netherlands, is one such visionary pioneer. With a keen focus on power reduction in frequency synthesizers, Vlachogiannakis has made significant contributions through his patented inventions and collaborations.

Latest Patents:

Vlachogiannakis has demonstrated his expertise by securing two remarkable patents. His first groundbreaking invention is a "Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-to-Time and Time-to-Digital Circuit Pair." This patent showcases the integration of a novel look-ahead time-to-digital converter (TDC) into an all-digital phase-locked loop (ADPLL). By leveraging the deterministic nature of the phase error during frequency/phase lock, Vlachogiannakis achieves a substantial reduction in power consumption of the TDC. Additionally, the cyclic DTC-TDC pair circuit effectively diminishes fractional spurs of the output spectrum in near-integer channels through random rotations and averaging of mismatched elements. The ADPLL utilizes the look-ahead TDC and/or cyclic DTC-TDC pair circuitry.

Vlachogiannakis' second patent pertains to a "Fractional-N All Digital Phase-Locked Loop Incorporating Look Ahead Time-to-Digital Converter." This invention highlights the same novel look-ahead TDC, which serves as the fractional phase error detector within an ADPLL. By capitalizing on the deterministic nature of phase errors during frequency/phase lock, Vlachogiannakis again accomplishes a remarkable reduction in power consumption of the TDC. The cyclic DTC-TDC pair circuitry once more plays a significant role in minimizing fractional spurs of the output spectrum in near-integer channels. The associated rotation and dithering methods further enhance the efficiency of the ADPLL.

Career Highlights:

Vlachogiannakis has made significant strides in his career, demonstrating his expertise and dedication to innovation in the field of frequency synthesizers. As a valued member of Short Circuit Technologies LLC, Vlachogiannakis has brought his extensive knowledge and inventive mindset to the company, contributing to their advancements in this domain.

Collaborations:

Within the realm of frequency synthesizers, Vlachogiannakis has collaborated with esteemed professionals in similar fields. Augusto Ronchini Ximenes and Robert Bogdan Staszewski stand as notable coworkers who have shared their insights and expertise.

Conclusion:

Gerasimos S Vlachogiannakis has cemented his name as a remarkable innovator in the field of frequency synthesizers, particularly focusing on power reduction. His patented inventions demonstrate his profound understanding of phase-locked loops, time-to-digital converters, and their integration into all-digital systems. Through his collaborations and valuable contributions to Short Circuit Technologies LLC, Vlachogiannakis continues to shape the landscape of frequency synthesizers and drive future technological advancements in this field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…