Minneapolis, MN, United States of America

Geraldo Pradipta

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Nvidia Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Geraldo Pradipta. Retrieved from https://idiyas.com/inventor/geraldo-pradipta

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Geraldo Pradipta: Applying Self-Supervised Learning to Circuit Design

Introduction

Geraldo Pradipta is an inventor based in Minneapolis, Minnesota, and works at NVIDIA Corporation. His patent work explores how machine learning can help transform circuit netlists and guide decisions about gate sizing.

Latest Patents

Pradipta is named on one patent, Generative Self-Supervised Learning to Transform Circuit Netlists. The invention applies self-supervised machine learning to combinational gate sizing using an input circuit netlist. It describes a transformer neural network that selects gate sizes along paths connecting primary inputs and outputs, as well as sequential logic elements. These selections can be optimized for path delay, power consumption, and circuit area. His reported patent total is 1 patent.

Career Highlights

Pradipta’s disclosed patent work brings transformer-based machine learning to a circuit-design problem: choosing gate sizes while balancing performance, power, and area. He is associated with NVIDIA Corporation.

Collaborations

The patent information provided also names Siddhartha Nath and Haoxing Ren as Pradipta’s coworkers. Their inclusion reflects a connection to NVIDIA’s broader engineering and invention community.

Conclusion

Geraldo Pradipta’s patent illustrates an approach to using self-supervised learning and transformer networks to support circuit optimization, with gate sizing evaluated across delay, power, and area.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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