The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2026
Filed:
May. 27, 2022
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Siddhartha Nath, San Jose, CA (US);
Haoxing Ren, Austin, TX (US);
Geraldo Pradipta, Minneapolis, MN (US);
Corey Hu, San Diego, CA (US);
Tian Yang, Los Altos, CA (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 18/21 (2023.01); G06F 30/394 (2020.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 18/2185 (2023.01); G06F 30/394 (2020.01); G06N 20/00 (2019.01);
Abstract
Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.