Gerald Taylor

Title: Gerald Taylor - Innovator in Circuit Design Verification

Introduction

Gerald Taylor is a notable inventor based in Portland, OR (US). He has made significant contributions to the field of circuit design verification. His innovative approach has led to the development of a unique patent that enhances the efficiency of circuit design validation.

Latest Patents

Gerald Taylor holds a patent titled "Efficient execution of alternating automaton representing a safety assertion for a circuit." This patent describes a system that receives a circuit design and a description of its behavior specified as assertions. The system generates a model used for verifying that the circuit design satisfies the specified behavior. It creates an alternating automaton representing the assertions, which may be non-deterministic. The system translates this automaton to a finite state machine (FSM) that can be represented using a register transfer level (RTL) representation. By modeling existential transitions in the state machine using variables, the system generates fewer states, thereby requiring significantly less memory for processing the assertion. Ultimately, the system validates the circuit design for further design and manufacture.

Career Highlights

Gerald Taylor is currently employed at Synopsys, Inc., where he continues to work on innovative solutions in circuit design. His expertise in the field has made him a valuable asset to the company. He has demonstrated a commitment to advancing technology through his inventive work.

Collaborations

Gerald collaborates with Eduard Rudolf Cerny, contributing to the development of cutting-edge technologies in circuit design verification.

Conclusion

Gerald Taylor's contributions to circuit design verification through his patent and work at Synopsys, Inc. highlight his role as an innovator in the field. His efforts continue to shape the future of circuit design and validation.