Eindhoven, Netherlands

Georg Parteder

This inventor holds 1 USPTO granted patent. Top assignee: Ams Ag. Active years: 2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Georg Parteder. Retrieved from https://idiyas.com/inventor/georg-parteder-wc2ppb18

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2023

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1 patent (USPTO):Explore Patents

Title: Georg Parteder: Innovator in Semiconductor Technology

Introduction

Georg Parteder is a notable inventor based in Eindhoven, Netherlands. He has made significant contributions to the field of semiconductor technology, particularly through his innovative patent.

Latest Patents

Georg Parteder holds a patent titled "Method of forming a through-substrate via and a semiconductor device comprising a through-substrate via." This patent describes a process involving a substrate that is equipped with a dielectric, a metal layer embedded within the dielectric, and a metallic layer positioned on the metal layer. The invention details the formation of a via hole in the substrate and the dielectric, along with the application of an insulation layer and subsequent metallization in the via hole.

Career Highlights

Georg Parteder is currently employed at AMS AG, a company known for its expertise in sensor solutions and analog ICs. His work has led to advancements in semiconductor devices, showcasing his commitment to innovation in this critical technology sector.

Collaborations

Throughout his career, Georg has collaborated with talented professionals such as Jochen Kraft and Stefan Jessenig. These collaborations have further enriched his work and contributed to the development of cutting-edge technologies.

Conclusion

Georg Parteder's contributions to semiconductor technology through his patent and work at AMS AG highlight his role as an influential inventor in the field. His innovative methods continue to shape the future of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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