Gaurav G Mehta

Title: Gaurav G Mehta: Innovator in Power Consumption Reduction

Introduction

Gaurav G Mehta is a notable inventor based in San Jose, CA. He has made significant contributions to the field of electronics, particularly in reducing power consumption in logic circuits. With a total of 3 patents to his name, Mehta's work is recognized for its innovative approaches to improving efficiency in electronic devices.

Latest Patents

One of his latest patents is titled "Method and apparatus for reducing power consumption in a domino logic." This invention provides a method for determining the first state of an output from an upstream logic block and modifying the domino logic block accordingly. This modification prevents unnecessary toggling of the output, thereby conserving power. Another significant patent is "Pulsed domino latches," which introduces a novel method for interfacing static logic to domino logic. This invention allows the domino evaluation tree to operate only during a brief window of time, enhancing the stability and efficiency of the logic circuit.

Career Highlights

Gaurav G Mehta is currently employed at Intel Corporation, where he continues to innovate and develop new technologies. His work at Intel has positioned him as a key player in the advancement of electronic design and power management.

Collaborations

Mehta has collaborated with notable colleagues, including David N Harris and S Deo Singh. These collaborations have contributed to the development of cutting-edge technologies in the field of electronics.

Conclusion

Gaurav G Mehta's contributions to the field of electronics, particularly in power consumption reduction, highlight his innovative spirit and dedication to advancing technology. His patents reflect a commitment to improving efficiency in electronic devices, making a significant impact in the industry.