Westford, MA, United States of America

Garima Jain

This inventor holds 1 USPTO granted patent. Top assignee: Dell Products Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Garima Jain. Retrieved from https://idiyas.com/inventor/garima-jain-g4crnvee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Garima Jain - Innovator in Storage Node Performance Analysis

Introduction

Garima Jain is a talented inventor based in Westford, MA (US). She has made significant contributions to the field of technology, particularly in analyzing storage node performance problems. Her innovative approach utilizes thread CPU utilization patterns to enhance system efficiency.

Latest Patents

Garima Jain holds a patent titled "Using thread CPU utilization patterns to analyze storage node performance problems." This patent focuses on monitoring per-thread CPU cycle utilization statistics and counting code path utilizations. By employing time-series clustering, she identifies code path activity clusters and thread clusters with similar CPU cycle utilization patterns. The most active code paths are selected from each cluster, and the thread clusters that correlate with these code paths are ranked based on CPU cycle utilization.

Career Highlights

Garima Jain is currently employed at Dell Products Inc., where she continues to innovate and contribute to advancements in technology. Her work has been instrumental in improving the performance of storage arrays, making her a valuable asset to her team and the company.

Collaborations

Garima has collaborated with notable coworkers, including Pankaj Soni and Ramesh Doddaiah. Their teamwork has fostered an environment of innovation and creativity, leading to impactful developments in their field.

Conclusion

Garima Jain is a remarkable inventor whose work in analyzing storage node performance through CPU utilization patterns showcases her expertise and dedication to technological advancement. Her contributions are paving the way for more efficient storage solutions in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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