The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Jan. 08, 2024
Applicant:

Dell Products L.p., Hopkinton, MA (US);

Inventors:

Pankaj Soni, Sikar, IN;

Ramesh Doddaiah, Westborough, MA (US);

Malak Alshawabkeh, Franklin, MA (US);

Eddie Tran, Lowell, MA (US);

Garima Jain, Westford, MA (US);

Assignee:

Dell Products L.P., Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 11/0715 (2013.01); G06F 11/0727 (2013.01);
Abstract

Thread CPU cycle utilization patterns are used to analyze storage array performance problems. Per-thread CPU cycle utilization statistics are monitored, and code path utilizations are counted. Time-series clustering is used to identify code path activity clusters and thread clusters having similar CPU cycle utilization patterns. The most active code paths are selected from each code path activity cluster. The thread clusters that are most highly correlated with the selected code paths are selected and ranked based on CPU cycle utilization.


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