Gang Chen

Title: Gang Chen: Innovator in PMOS Device Testing

Introduction

Gang Chen is a notable inventor based in Singapore, SG. He has made significant contributions to the field of semiconductor technology, particularly in the testing of PMOS devices. With a total of 2 patents, his work has advanced the understanding and reliability of electronic components.

Latest Patents

One of Gang Chen's latest patents is a test structure for automatic dynamic negative-bias temperature instability testing. This invention describes a novel test structure and process designed to perform automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter ensures the proper 180-degree phase relationship between the test device source and gate voltage, while the embedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUTs).

Career Highlights

Gang Chen is currently employed at Chartered Semiconductor Manufacturing Ltd, where he continues to innovate in the semiconductor industry. His work has been pivotal in enhancing the performance and reliability of PMOS devices.

Collaborations

Some of his notable coworkers include Chew Hoe Ang and Shyue Seng Tan, who have collaborated with him on various projects within the semiconductor field.

Conclusion

Gang Chen's contributions to the field of semiconductor technology, particularly through his innovative patents, have made a lasting impact on the industry. His work continues to influence the development of reliable electronic components.