Chapel Hill, NC, United States of America

Günter Gerstmeier

This inventor holds 1 USPTO granted patent. Top assignee: Infineon Technologies Ag. Active years: 2003.


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: Günter Gerstmeier: Innovator in Integrated Circuit Technology

Introduction

Günter Gerstmeier is a notable inventor based in Chapel Hill, NC (US). He has made significant contributions to the field of semiconductor technology, particularly in the design of integrated circuits. His innovative approach has led to advancements that enhance the testing capabilities of transistors.

Latest Patents

Günter Gerstmeier holds a patent for an "Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration." This patent focuses on circuit configurations for testing transistors arranged in the scribe line between integrated circuits on a semiconductor wafer. The design aims to increase the number of testable transistors while minimizing surface area. The transistors are organized in a matrix with at least two rows, optimizing their connections to pads for efficient testing.

Career Highlights

Günter has had a successful career at Infineon Technologies AG, where he has been instrumental in developing cutting-edge semiconductor solutions. His work has contributed to the advancement of integrated circuit technology, making significant impacts in the industry.

Collaborations

Günter Gerstmeier has collaborated with various professionals in the field, including his coworker Valentin Rosskopf. Their joint efforts have furthered the development of innovative technologies in semiconductor design.

Conclusion

Günter Gerstmeier's contributions to integrated circuit technology exemplify the spirit of innovation in the semiconductor industry. His patent and work at Infineon Technologies AG highlight his role as a key figure in advancing testing methodologies for transistors.

Profile summary based on public USPTO records.
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