The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2003

Filed:

Jun. 07, 2001
Applicant:
Inventors:

Günter Gerstmeier, Chapel Hill, NC (US);

Valentin Rosskopf, Poettmes, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/126 ;
U.S. Cl.
CPC ...
G01R 3/126 ;
Abstract

Circuit configurations for testing transistors are arranged in the scribe line between integrated circuits on a semiconductor wafer. In order to increase the number of testable transistors while consuming little surface area, the transistors are arranged in a matrix in at least two rows. The drain-source paths of the transistors in the first row are connected between pads, and their gate connections are connected to a common pad. The drain-source paths of the transistors in the second row are connected firstly to one of the pads, and are secondly jointly connected to a further pad. Their gate connections are likewise connected to a further pad. The matrix-like arrangement of the transistors can be extended by using additional rows.


Find Patent Forward Citations

Gerstmeier, Günter. (2003). Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration (U.S. Patent No. 6529031). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6529031

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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