Hsinchu, Taiwan

Fu-Yi Liu

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fu-Yi Liu. Retrieved from https://idiyas.com/inventor/fu-yi-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Fu-Yi Liu and His Patent for Dry-Etching Systems

Introduction

Fu-Yi Liu is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work addresses equipment design for semiconductor wafer processing.

Latest Patents

Liu is listed as an inventor on 1 patent, titled “Methods and Systems for Dry Etching.” The patent describes a wafer clamp ring with a central opening for substrate treatment and tapered outer support holes that receive pins from plunger assemblies. The tapered holes help reduce horizontal shifting as the ring moves during operation, which can improve wafer yield near the edges.

Career Highlights

Liu’s documented patent contribution focuses on a mechanical feature intended to stabilize wafer-handling equipment during dry etching. The patent connects this design improvement with the practical goal of reducing edge-related wafer defects.

Collaborations

The patent lists Chou Feng Li and Chih-Hsien Hsu among Liu’s fellow inventors. Their collaboration reflects a shared contribution to the disclosed dry-etching system.

Conclusion

Fu-Yi Liu’s patent highlights how a targeted equipment-design improvement can support more stable wafer processing and better yield at wafer edges.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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