Hsinchu, Taiwan

Fu-Tsai Chen

This inventor holds 1 USPTO granted patent. Top assignee: Silicon Integrated Systems Corporation. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fu-Tsai Chen. Retrieved from https://idiyas.com/inventor/fu-tsai-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Fu-Tsai Chen: Innovator in Load Board Technology

Introduction

Fu-Tsai Chen is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of integrated circuit testing. His innovative approach has led to the development of a unique load board that enhances the efficiency of packaged IC testing.

Latest Patents

Fu-Tsai Chen holds 1 patent for his invention titled "Load board - A load board for packaged IC testing." This load board features predetermined testing circuits and bonding pad areas on its surface. A plurality of bonding pads is formed on these areas, each corresponding to a lead of a packaged IC for testing connection. This design allows for direct connection of the leads during IC testing, eliminating the need for a conventional test socket.

Career Highlights

Fu-Tsai Chen is currently employed at Silicon Integrated Systems Corporation, where he continues to innovate in the field of semiconductor technology. His work has been instrumental in advancing testing methodologies for integrated circuits.

Collaborations

Some of his notable coworkers include Hsiu-Chu Chou and Mu-Sheng Liao. Their collaborative efforts contribute to the ongoing success and innovation within their organization.

Conclusion

Fu-Tsai Chen's contributions to load board technology exemplify his commitment to improving integrated circuit testing. His innovative designs continue to influence the industry and enhance testing efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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