The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2006
Filed:
Aug. 11, 2003
Ching-jung Huang, Hsinchu, TW;
Hsiu-chu Chou, Hsinchu, TW;
Mu-sheng Liao, Hsinchu, TW;
Fu-tsai Chen, Hsinchu, TW;
Pao-chuan Kuo, Kaohsiung, TW;
Ching-Jung Huang, Hsinchu, TW;
Hsiu-Chu Chou, Hsinchu, TW;
Mu-Sheng Liao, Hsinchu, TW;
Fu-Tsai Chen, Hsinchu, TW;
Pao-Chuan Kuo, Kaohsiung, TW;
Silicon Integrated Systems Corp., Hsinchu, TW;
Abstract
A load board for packaged IC testing. The load board with predetermined testing circuit thereon has bonding pad areas on its surface. A plurality of bonding pads is formed on the bonding pad areas, each of which is disposed corresponding to a lead of a packaged IC for testing connection, such as a quad flat packaged IC (QFP), a dual inline packaged IC (DIP) or a small outline packaged IC (SOP). The bonding pads on the load board connect the leads of the testing IC directly during IC testing, thus the conventional test socket between a conventional load board and a packaged IC is omitted.