San Jose, CA, United States of America

Fei Lu

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignees: Marvell Asia Pte., Ltd., Pq Labs, Inc.. Active years: 2013-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fei Lu. Retrieved from https://idiyas.com/inventor/fei-lu-fm9digd0

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 2.1

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2013-2026

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3 patents (USPTO):Explore Patents

Title: Fei Lu: Inventor of Integrated Circuit and High-Speed Serial Technologies.

Introduction

Fei Lu is an inventor based in San Jose, California. His patent work includes integrated circuit designs that address terminal sharing and noise isolation, as well as oscillator technology for high-speed serial devices. He has 3 patents.

Latest Patents

“Power Terminal Sharing with Noise Isolation” describes an integrated circuit in which multiple functional circuits share access to a terminal. Individual isolation circuits help prevent noise from one circuit from coupling through the shared terminal into another.

“Oscillator for High-Speed Serial Device” concerns transceiver circuitry that connects a functional circuit to a transmission medium. Its clock-generation circuitry includes an oscillator with transconductance circuitry, a capacitance element, and multiple parallel inductors. The inductor arrangement produces magnetic flux in opposing directions, supporting the oscillator design.

Career Highlights

Lu’s listed company affiliations include Marvell Asia Pte. Ltd. and PQ Labs, Inc. His patent portfolio reflects work on circuit architecture and clock generation for communications technology.

Collaborations

Among Lu’s listed coworkers are Yuxiang Sun and Hui Zhao.

Conclusion

Fei Lu’s inventions address practical challenges in integrated circuits and high-speed communications, with a focus on noise isolation and oscillator design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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