The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Sep. 28, 2022
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Hui Zhao, San Jose, CA (US);

Fei Lu, San Jose, CA (US);

Yuxiang Sun, San Jose, CA (US);

Zhendong Guo, San Jose, CA (US);

Assignee:

MARVELL ASIA PTE LTD, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01L 23/552 (2006.01); H03H 7/01 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/525 (2013.01); H01L 23/5286 (2013.01); H01L 23/552 (2013.01); H01L 24/14 (2013.01); H03H 7/0153 (2013.01); H03H 7/1741 (2013.01); H01L 2224/14152 (2013.01); H01L 2224/14153 (2013.01); H01L 2224/14515 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/30107 (2013.01); H01L 2924/3025 (2013.01);
Abstract

An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.


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