Fei Chen

Title: Fei Chen - Innovator in Data-Driven Logic Simulation

Introduction

Fei Chen is a prominent inventor based in Newark, DE (US). He has made significant contributions to the field of logic simulation, holding a total of 3 patents. His work focuses on developing advanced methods and systems for logic verification and simulation.

Latest Patents

Fei Chen's latest patents include innovative technologies that enhance the efficiency of hardware logic designs. One of his notable inventions is a data-driven logic simulation apparatus and method. This technology compiles hardware logic designs into data-driven logic programs that can be executed on a specialized chip. The apparatus features a storage library for defining a net-list synthesized by a synthesis tool, along with a data-driven logic verification chip that comprises multiple logic processors. Additionally, it includes a code generator that utilizes heuristics to convert the net-list into data-driven logic programs, effectively balancing computing and storage loads across the logic processors.

Another significant patent involves systems and methods for logic verification. This invention translates logic designs into executable code for a multi-processor-based parallel logic simulation device. The system implements various parallel execution methods, including IPMD, MPMD, and DDMT, to enhance the simulation process.

Career Highlights

Fei Chen is currently employed at Et International, Inc., where he continues to innovate in the field of logic simulation. His expertise and dedication to advancing technology have positioned him as a key figure in his industry.

Collaborations

Fei Chen collaborates with Guang R Gao, leveraging their combined knowledge and skills to push the boundaries of logic simulation technology.

Conclusion

Fei Chen's contributions to data-driven logic simulation and verification are noteworthy, showcasing his commitment to innovation in technology. His patents reflect a deep understanding of complex systems and a drive to improve hardware logic design processes.