The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2011
Filed:
Nov. 09, 2007
Applicants:
Guang R. Gao, Newark, DE (US);
Fei Chen, Newark, DE (US);
Inventors:
Guang R. Gao, Newark, DE (US);
Fei Chen, Newark, DE (US);
Assignee:
ET International, Inc., Newark, DE (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.
Gao, Guang. (2011). Systems and methods for logic verification (U.S. Patent No. 7934179). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7934179
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile