San Jose, CA, United States of America

Fatha Khalsa

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Nxp B.v.. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fatha Khalsa. Retrieved from https://idiyas.com/inventor/fatha-khalsa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Fatha Khalsa: Semiconductor Chip-System Inventor

Introduction

Fatha Khalsa is an inventor based in San Jose, California, whose patent work addresses the design and packaging of high-bandwidth semiconductor systems. He is associated with NXP B.V. and is credited with 1 patent.

Latest Patents

Khalsa’s patent, “Impedance Optimized Chip System,” describes dividing a high-bandwidth circuit into portions for implementation on separate semiconductor chips. The method generates die bond-pad arrangements and chip locations in relation to package parameters and the package’s input/output arrangement. It aims to establish bond-wire lengths that meet specified characteristic-impedance requirements. The patent also describes boundary parameters for segmentation, including limits on the number of portions and, optionally, chip area.

Career Highlights

Khalsa’s documented patent contribution focuses on coordinating circuit segmentation, chip placement, and bond-wire design. These considerations are relevant to developing semiconductor packages that meet electrical and physical design constraints.

Collaborations

Khalsa’s listed coworkers include Dominicus M. Roozeboom and James Raymond Spehar. His company affiliation is NXP B.V.

Conclusion

Fatha Khalsa’s patent highlights an approach to optimizing semiconductor chip systems by aligning circuit segmentation and package layout with impedance requirements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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