The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Apr. 09, 2010
James Raymond Spehar, Chandler, AZ (US);
Christian Paquet, Cupertino, CA (US);
Wayne A. Nunn, Hidden Valley Lake, CA (US);
Dominicus M. Roozeboom, San Jose, CA (US);
Joseph E. Schulze, Chandler, AZ (US);
Fatha Khalsa, San Jose, CA (US);
James Raymond Spehar, Chandler, AZ (US);
Christian Paquet, Cupertino, CA (US);
Wayne A. Nunn, Hidden Valley Lake, CA (US);
Dominicus M. Roozeboom, San Jose, CA (US);
Joseph E. Schulze, Chandler, AZ (US);
Fatha Khalsa, San Jose, CA (US);
NXP B.V., Eindhoven, NL;
Abstract
A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.