Palo Alto, CA, United States of America

Eshan Singh

This inventor holds 1 USPTO granted patent and 1 EPO patent. Top assignees: Leland Stanford Junior University, New York University. Active years: 2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Eshan Singh. Retrieved from https://idiyas.com/inventor/eshan-singh-o8yozl74

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

 

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2020

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1 patent (USPTO):Explore Patents

Title: Eshan Singh: Innovator in Integrated Circuit Verification

Introduction

Eshan Singh is a prominent inventor based in Palo Alto, CA. He has made significant contributions to the field of integrated circuit verification, particularly through his innovative patent in post-silicon validation and debugging.

Latest Patents

Eshan Singh holds a patent titled "Post-silicon validation and debug using symbolic quick error detection." This patent discloses improved methods and structures for verifying integrated circuits, specifically systems-on-a-chip (SoC). The methods and structures introduced in this patent, referred to as Symbolic Quick Error Detection (Symbolic QED), offer several key characteristics. Symbolic QED is applicable to any SoC design that includes at least one programmable processor. It is broadly applicable for logic bugs within processor cores, accelerators, and uncore components. Notably, it does not require failure reproduction, human intervention during bug localization, trace buffers, or assertions. Additionally, it utilizes hardware structures known as 'change detectors,' which introduce minimal area overhead. Symbolic QED provides a systematic and automated approach to inserting change detectors during the design phase, enabling quick error detection tests that identify bugs with short latencies and high coverage. Furthermore, it employs formal techniques for bug localization and the generation of minimal bug traces upon bug detection.

Career Highlights

Eshan Singh has worked at prestigious institutions, including Leland Stanford Junior University and New York University. His experience in these environments has contributed to his expertise in integrated circuit design and verification.

Collaborations

Eshan has collaborated with notable individuals in his field, including Subhasish Mitra and Clark Barrett. Their joint efforts have further advanced the research and development of innovative verification methods.

Conclusion

Eshan Singh's contributions to integrated circuit verification through his patent on Symbolic Quick Error Detection highlight his innovative spirit and dedication to improving technology. His work continues to influence the field and pave the way for future advancements in integrated circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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