The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2020
Filed:
Jun. 06, 2016
The Board of Trustees of the Leland Stanford Junior University, Palo Alto, CA (US);
New York University, New York, NY (US);
Subhasish Mitra, Palo Alto, CA (US);
Clark Barrett, Palo Alto, CA (US);
David Lin, Palo Alto, CA (US);
Eshan Singh, Palo Alto, CA (US);
The Board of Trustees of the Leland Stanford Junior University, Stanford, CA (US);
New York University, New York, NY (US);
Abstract
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called 'change detectors' which introduce only a small area overhead. Symbolic QED exhibits: 1) A systematic (and automated) approach to inserting 'change detectors' during a design phase; 2) Quick Error Detection (QED) tests that detect bugs with short error detection latencies and high coverage; and 3) Formal techniques that enable bug localization and generation of minimal bug traces upon bug detection.