Palo Alto, CA, United States of America

Clark Barrett

This inventor holds 1 USPTO granted patent and 1 published patent application and 1 EPO patent. Top assignees: Leland Stanford Junior University, New York University. Active years: 2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Clark Barrett. Retrieved from https://idiyas.com/inventor/clark-barrett

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

 

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2020

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1 patent (USPTO):Explore Patents

Title: Clark Barrett: Innovator in Post-Silicon Validation

Introduction

Clark Barrett is a prominent inventor based in Palo Alto, California. He is known for his significant contributions to the field of integrated circuit verification. His innovative approach has led to the development of advanced methods for validating systems-on-a-chip.

Latest Patents

Clark Barrett holds a patent titled "Post-silicon validation and debug using symbolic quick error detection." This patent discloses improved methods and structures for verifying integrated circuits, particularly systems-on-a-chip. The methods, referred to as Symbolic Quick Error Detection (Symbolic QED), offer several key characteristics. They are applicable to any System-on-Chip design that includes at least one programmable processor. Symbolic QED is broadly applicable for logic bugs within processor cores, accelerators, and uncore components. Notably, it does not require failure reproduction or human intervention during bug localization. Additionally, it does not necessitate trace buffers or assertions, and it employs hardware structures called 'change detectors' that introduce minimal area overhead. Symbolic QED provides a systematic and automated approach to inserting change detectors during the design phase. It also features Quick Error Detection tests that identify bugs with short detection latencies and high coverage, along with formal techniques for bug localization and generating minimal bug traces upon detection.

Career Highlights

Throughout his career, Clark Barrett has worked at prestigious institutions, including Leland Stanford Junior University and New York University. His work has significantly impacted the field of integrated circuit design and verification.

Collaborations

Clark Barrett has collaborated with notable individuals in his field, including Subhasish Mitra and David Lin. Their collective expertise has contributed to advancements in the verification of integrated circuits.

Conclusion

Clark Barrett is a distinguished inventor whose work in post-silicon validation has paved the way for more efficient and reliable integrated circuit designs. His innovative methods continue to influence the industry and enhance the verification process for systems-on-a-chip.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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