Hillsboro, OR, United States of America

Erik W Peter

This inventor holds 6 USPTO granted patents and 1 published patent application and 1 EPO patent. Top assignee: Intel Corporation. Active years: 2001-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Erik W Peter. Retrieved from https://idiyas.com/inventor/erik-w-peter

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 

% Patents Active = 83.3

 

Average Co-Inventor Count = 2.7

ph-index = 4

Forward Citations = 51(Granted Patents)


Company Filing History:


Years Active: 2001-2018

Loading Chart...
Loading Chart...
6 patents (USPTO):Explore Patents

Title: The Innovations of Erik W Peter

Introduction

Erik W Peter is a notable inventor based in Hillsboro, OR (US). He has made significant contributions to the field of hybrid memory architectures. With a total of 6 patents to his name, Erik has established himself as a key figure in the technology sector.

Latest Patents

Among his latest patents, Erik has developed methods and apparatuses for providing a hybrid memory module that incorporates both volatile and non-volatile memories. This innovation aims to replace a DDR channel in a processing system, showcasing his commitment to advancing memory technology.

Career Highlights

Erik W Peter is currently employed at Intel Corporation, where he continues to push the boundaries of memory architecture. His work has been instrumental in enhancing the efficiency and performance of processing systems.

Collaborations

Throughout his career, Erik has collaborated with talented individuals such as Kumar K Chinnaswamy and Randy B Osborne. These partnerships have contributed to the successful development of innovative technologies.

Conclusion

Erik W Peter's contributions to hybrid memory architectures and his ongoing work at Intel Corporation highlight his importance in the field of technology. His innovations continue to shape the future of memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…