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For the Inventor, By the Inventor

San Jose, CA, United States of America

Enric Musoll

This inventor holds 15 USPTO granted patents and 1 EPO patent. Top assignees: Mips Technologies, Inc., Xpliant, Inc., Cavium, Inc.. Active years: 2006-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Enric Musoll. Retrieved from https://idiyas.com/inventor/enric-musoll

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 86.7


Average Co-Inventor Count = 3.5

ph-index = 6

Forward Citations = 164(Granted Patents)


Company Filing History:

goldMedal8 out of 271 
 
Mips Technologies, Inc.
 patents
silverMedal5 out of 10 
 
Xpliant, Inc.
 patents
bronzeMedal1 out of 448 
 
Cavium, Inc.
 patents
4. 1 out of 1,234 
 
Marvell Asia Pte., Ltd.
 patents

Years Active: 2006-2023

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15 patents (USPTO):Explore Patents
1. 11621923 - Queueing system with head-of-line block avoidance (2023-04-04),
2. 9736069 - Method for storing and retrieving packets in high bandwidth and low latency packet processing devices (2017-08-15),
3. 9509585 - Apparatus and method for time stamping packets across several nodes in a network (2016-11-29),
4. 9438539 - Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches (2016-09-06),
5. 9262369 - Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed (2016-02-16),
6. 9256380 - Apparatus and method for packet memory datapath processing in high bandwidth packet processing devices (2016-02-09),
7. 9009364 - Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed (2015-04-14),
8. 7715410 - Queueing system for processors in packet routing operations (2010-05-11),
9. 7661112 - Methods and apparatus for managing a buffer of events in the background (2010-02-09),
10. 7551626 - Queueing system for processors in packet routing operations (2009-06-23),
11. 7502876 - Background memory manager that determines if data structures fits in memory with memory state transactions map (2009-03-10),
12. 7237093 - Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams (2007-06-26),
13. 7058064 - Queueing system for processors in packet routing operations (2006-06-06),
14. 7035997 - Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors (2006-04-25),
15. 7032226 - Methods and apparatus for managing a buffer of events in the background (2006-04-18),

Title: The Innovative Mind of Enric Musoll

Introduction: Enric Musoll, a talented inventor based in San Jose, CA, is known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Enric Musoll's latest patents include a cutting-edge software application for enhancing cybersecurity measures in cloud computing systems and a revolutionary device for optimizing energy efficiency in smart homes.

Career Highlights: With over two decades of experience in the tech industry, Enric Musoll has held key positions in various renowned tech companies, where he spearheaded the development of innovative solutions that have reshaped the industry.

Collaborations: Throughout his career, Enric Musoll has collaborated with leading engineers, designers, and researchers to bring his visionary ideas to life. His collaborative efforts have resulted in the creation of groundbreaking products that have received international acclaim.

Conclusion: Enric Musoll's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a trailblazer in the world of technology. His remarkable contributions continue to inspire future generations of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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