Mips Technologies, Inc.

Xpliant, Inc.

Marvell Asia Pte., Ltd.

Cavium, Inc.

Enric Musoll

Mario D Nemirovsky

Tsahi Daniel

Adolfo M Nemirovsky

Narendra Sankar

Dan Tu

Sridevi Polasanapalli

Stephen Melvin

Nandakumar Sampath

Avinash Sodani

Chia-Hsin Chen

Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.

Queueing system with head-of-line block avoidance

A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.

Method for storing and retrieving packets in high bandwidth and low latency packet processing devices

A method includes receiving a packet at an ingress node of a network. A hierarchical time stamp is created in the packet by the ingress node. The hierarchical time stamp includes an initial time stamp and an initial node identifier. The packet is passed to another network node, which adds a subsequent time stamp and a subsequent node identifier to the hierarchical time stamp. The packet is received at an egress node of the network. A final time stamp and a final node identifier are added to the hierarchical time stamp at the egress node. The hierarchical time stamp is then removed from the packet and the packet is passed to another network. The hierarchical time stamp is delivered to an analyzer.

Apparatus and method for time stamping packets across several nodes in a network

A packet processor includes a packet memory manager configured to receive a single header reference count and a single payload reference count for a packet. A page link list walk for the header under the control of the header reference count is performed in parallel with a page link list walk for the payload under the control of the payload reference count.

Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches

A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed

A method of processing packets includes receiving packets and assigning the packets to different pages, where each page represents a fixed amount of memory. The different pages are distributed to different pools, where each pool has a unique mapping to banks, and where each bank is a set of memory resources. The different pages from the different pools are assigned to different banks in accordance with the unique mapping.

Apparatus and method for packet memory datapath processing in high bandwidth packet processing devices

In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.

Queueing system for processors in packet routing operations

A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.

Methods and apparatus for managing a buffer of events in the background

In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. The BMM manages the memory, determining if each data structure fits into the memory, deciding exactly where to place the data structure in memory, performing all data transfers between the outside device and the memory, and maintaining the memory state map according to memory transactions made, and informing the processor of new data and its location. In preferred embodiments the BMM, in the process of storing data structures into the memory, provides an identifier for each structure to the processor. The system is particularly applicable to Internet packet processing in packet routers.

Background memory manager that determines if data structures fits in memory with memory state transactions map

In a multi-streaming processor having a memory cache, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and a hit/miss predictor for forecasting whether a load instruction will hit or miss the cache. The prediction by the hit-miss predictor is used by the fetch algorithm in determining from which stream to fetch. A hit prediction results in a next instruction being fetched from the same stream as the instruction tested by the hit/miss predictor, while a miss prediction results in the next instruction being fetched from a different stream, if any. The predictor is also used to determine which instructions to dispatch to functional units.

Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams

In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the cache or a branch will be taken. The prediction or predictions are used by the fetch algorithm in determining from which stream to fetch. In some cases probabilities are determined and also used in decisions, and predictors may be used at either or both of fetch and dispatch stages.

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San Jose, CA, United States of America

Enric Musoll