Bengaluru, India

Doorlabh Panjwani

This inventor holds 3 USPTO granted patents and 2 published patent applications. Top assignee: International Business Machines Corporation. Active years: 2017-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Doorlabh Panjwani. Retrieved from https://idiyas.com/inventor/doorlabh-panjwani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 66.7

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 25(Granted Patents)


Location History:

  • Bengaluru, IN (2017 - 2019)
  • Karnataka, IN (2021)

Company Filing History:


Years Active: 2017-2021

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3 patents (USPTO):Explore Patents

Title: Innovations by Doorlabh Panjwani: Pioneering Semiconductor Testing

Introduction

Doorlabh Panjwani, based in Bengaluru, India, is a prominent inventor known for his innovative contributions to semiconductor testing technologies. With a total of three patents to his name, he has made significant strides in enhancing the efficiency and effectiveness of semiconductor testing methods.

Latest Patents

One of his notable inventions is in the field of 3D chip testing through a micro-C4 interface. He has developed structures and methods for directly testing a semiconductor wafer that incorporates micro-solder connections. According to one embodiment of his patent, a method is presented that forms a pattern of micro-solder connections coupled with through substrate vias (TSVs), which allows for direct electrical probing without the requirement of a testing interposer. Additionally, he has introduced a novel electrical probe tip structure that aligns the contacts on the same pitch as the micro-solder connections, enhancing the precision of the testing process.

Career Highlights

Doorlabh Panjwani is currently associated with the International Business Machines Corporation (IBM), where he plays a critical role in advancing semiconductor technologies. Through his work, he has contributed significantly to the company's innovative landscape, focusing on technology that underpins modern electronic devices.

Collaborations

Throughout his career, Doorlabh has collaborated with esteemed colleagues, including Victor Anthony Garibay and Chetan Mehta. Together, they have worked on pioneering solutions that push the boundaries of what is achievable in semiconductor testing and technology.

Conclusion

With his inventive spirit and dedication, Doorlabh Panjwani continues to lead advancements in semiconductor testing methods. His patents reflect a deep understanding of the technical intricacies involved in modern electronics, ensuring that his contributions will have a lasting impact on the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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