Bengaluru, India

Diganchal Chakraborty

This inventor holds 2 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2017-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Diganchal Chakraborty. Retrieved from https://idiyas.com/inventor/diganchal-chakraborty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.4

ph-index = 1

Forward Citations = 2(Granted Patents)


Location History:

  • Bengaluru, IN (2017)
  • Karnataka, IN (2023)

Company Filing History:


Years Active: 2017-2023

Loading Chart...
2 patents (USPTO):Explore Patents

Title: Diganchal Chakraborty and His Contributions to Electronic Design Verification

Introduction

Diganchal Chakraborty is an inventor based in Bengaluru, India, whose patent work focuses on methods for verifying electronic designs. His inventions address challenges in mixed-signal circuit modeling and the extraction of useful assertions from design signals and simulation traces. Chakraborty is associated with Synopsys, Inc., a company that develops software and services for semiconductor design and verification.

Latest Patents

Chakraborty’s listed patents include two inventions related to electronic design verification.

“Power Aware Real Number Modeling in Dynamic Verification of Mixed-Signal Integrated Circuit Design” describes a method for synchronizing different representations of a power supply in a mixed-signal design. The method identifies mismatches between a power supply network description and a register-transfer-level hardware description, generates a value converter, and uses it during runtime to translate voltage values between the descriptions. This approach helps maintain consistency when verifying designs that combine analog and digital circuit portions.

“Assertion Extraction from Design and Its Signal Traces” presents a method for generating verification assertions from groups of signals in an electronic design. It samples signal values over a fixed-depth temporal window, organizes the resulting combinations into truth tables, and extracts functional relationships that can be used to create assertions. The method then filters and checks the generated properties, producing syntactically correct assert, assume, and cover statements for further simulation, emulation, or formal verification.

Career Highlights

Chakraborty’s patent portfolio reflects work on improving verification workflows for complex semiconductor designs. His inventions address both power-aware modeling across mixed-signal descriptions and the systematic generation of properties from design behavior. The listed record attributes 2 patents to him.

Collaborations

Chakraborty’s listed coworkers include Harsh Chilwal and Saptarshi Ghosh. His patent work is associated with Synopsys, Inc., where these technical contributions relate to electronic design and verification.

Conclusion

Diganchal Chakraborty’s inventions focus on making electronic design verification more consistent and efficient, particularly through power-aware mixed-signal modeling and automated assertion generation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…