Hopkinton, MA, United States of America

Dawei Pan

This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dawei Pan. Retrieved from https://idiyas.com/inventor/dawei-pan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Dawei Pan: Inventor in Verification Technology

Introduction

Dawei Pan is an inventor based in Hopkinton, Massachusetts, and works at Synopsys, Inc. His patent work addresses techniques for detecting and responding to thread data races in parallel verification testbenches.

Latest Patents

The available information identifies one patent associated with Pan: Thread Data Race Detection and Synchronization for Parallel Implementation of Verification Testbenches. The invention describes a testbench whose components are organized into groups and executed on simulation threads. By logging memory accesses across component groups, a processing device can identify potential thread data races and trigger an appropriate response. The record lists 1 patent.

Career Highlights

Pan’s listed work at Synopsys connects his invention to electronic design automation and the verification of designs under test. The patent focuses on coordinating parallel testbench execution while monitoring memory access for race conditions.

Collaborations

The patent’s subject matter concerns testbench components and processing devices working together to detect race conditions during simulation. The available information does not identify additional collaborators.

Conclusion

Dawei Pan’s listed patent presents a method for detecting thread data races in parallel verification testbenches, reflecting his work in design verification at Synopsys, Inc.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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