Poughkeepsie, NY, United States of America

David Patrick Hillerud

This inventor holds 2 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 1997-2005.


% Patents Active = 100.0

Average Co-Inventor Count = 5.5

ph-index = 2

Forward Citations = 95(Granted Patents)


Company Filing History:


Years Active: 1997-2005

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2 patents (USPTO):Explore Patents

Title: David Patrick Hillerud: Innovator in Processor Recovery Systems

Introduction

David Patrick Hillerud is a notable inventor based in Poughkeepsie, NY (US). He has made significant contributions to the field of processor systems, particularly in enhancing their reliability and efficiency. With a total of 2 patents, Hillerud's work focuses on innovative methods for managing recovery units in processor systems.

Latest Patents

Hillerud's latest patents include two groundbreaking inventions. The first patent is titled "Write Before Read Interlock for Recovery Unit Operands." This invention describes a method for holding up recovery unit (R-unit) operands for a minimum number of cycles until all prior updates have completed. The method involves comparing addresses in at least one queue and interlocking valid R-unit register address matches. It includes receiving a plurality of R-unit register addresses and storing them in at least one queue, which consists of a write queue, a read queue, and a pre-write queue. The method requires accessing these queues and comparing the R-unit register addresses therein. If a valid match is found, one or more interlocks are implemented.

The second patent is titled "Recovery Unit for Mirrored Processors." This invention presents a method for making a processor system immune to circuit failure caused by external noise using mirrored processors. It includes a recovery unit integral with the method. Identical addresses and data information are generated in each of two processors. The data is partitioned into registers, and Error Correction Codes (ECCs) are generated for the data. The address, data, and ECC information for each processor are interlaced in a data structure. The interlaced structures of each processor are then compared. If no errors are detected, the data is checkpointed in the recovery unit. If an error is found, a recovery sequence can be initiated after the check-stop operation, restoring the system to the last error-free checkpointing operation.

Career Highlights

David Patrick Hillerud is currently employed at International Business Machines Corporation (IBM), where he continues to innovate in the field of processor technology. His work has been instrumental in developing systems that enhance the reliability of processors in various applications.

Collaborations

Hillerud has collaborated with notable colleagues, including Scott Barnett Swaney and Ferenc Miklos Bozso. These collaborations have contributed to the advancement of technology in the

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