Scarborough, ME, United States of America

David P Morrill

This inventor holds 10 USPTO granted patents and 1 published patent application. Top assignees: Fairchild Semiconductor Corporation, Other. Active years: 2000-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: David P Morrill. Retrieved from https://idiyas.com/inventor/david-p-morrill

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 10 

% Patents Active = 80.0

Average Co-Inventor Count = 1.1

ph-index = 5

Forward Citations = 62(Granted Patents)


Location History:

  • Portland, ME (US) (2000)
  • Scarborough, ME (US) (2000 - 2010)

Company Filing History:


Years Active: 2000-2010

Loading Chart...
10 patents (USPTO):Explore Patents

Title: David P Morrill: Innovator in Integrated Circuit Technology

Introduction

David P Morrill is a notable inventor based in Scarborough, ME (US), recognized for his contributions to integrated circuit technology. With a total of 10 patents to his name, Morrill has made significant advancements in the field, particularly in the areas of delay stabilization and ESD protection circuits.

Latest Patents

One of Morrill's latest patents is titled "Delay stabilization for skew tolerance." This invention addresses the challenges faced in integrated circuits that utilize multiple timing circuits, such as serializers and deserializers. The patent describes a method for developing a trim value correction factor that is applied during chip testing. This correction ensures that the VCO frequency of the serializer meets specifications while also allowing for adjustments to the delay between the received clock and data in the deserializer. The innovative aspect of this patent lies in the ability to store trim values on the integrated circuit itself.

Another significant patent by Morrill is the "Method of linearizing ESD capacitance." This invention focuses on an ESD protection circuit designed for input/output pads of integrated circuits. The circuit features discharge paths to both a power rail and ground, utilizing NMOS and PMOS transistors. The design compensates for voltage sensitivities in the drain capacitances, allowing for a more consistent capacitance load on the pad across varying voltage ranges. This advancement enhances the circuit's tolerance to overvoltages on the power rail.

Career Highlights

Throughout his career, David P Morrill has worked with prominent companies, including Fairchild Semiconductor Corporation. His experience in the semiconductor industry has equipped him with the knowledge and skills necessary to innovate in the field of integrated circuits.

Collaborations

Morrill has collaborated with various professionals, including Myron J Miske, to further his research and development efforts in integrated circuit technology.

Conclusion

David P Morrill's contributions to integrated circuit technology through his patents and career achievements highlight his role as an influential inventor in the field. His work continues to impact the development of advanced electronic systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…