North York, Canada

David MA

This inventor holds 1 USPTO granted patent, plus 2 CIPO patents. Top assignee: Microsemi Soc Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: David MA. Retrieved from https://idiyas.com/inventor/david-ma-uxws2d8a

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0


Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: David MA and RISC-V SoC Generation

Introduction

David MA is an inventor associated with North York, Canada, and Microsemi SOC Corporation. His work includes an invention for generating RISC-V system-on-chip designs that combine software processing with hardware acceleration.

Latest Patents

The provided information lists one patent for David MA: “High-Level Synthesis for RISC-V System-on-Chip Generation for Field Programmable Gate Arrays.” The patent describes a system that analyzes a code stream and divides its tasks between an open-standard processor and hardware accelerators implemented in reprogrammable hardware. It compiles the software portion into a binary and generates a hardware description for the accelerator portion, enabling both to exchange data while the code runs. This approach supports the generation of RISC-V-based SoCs for field-programmable gate arrays. 1 patent

Career Highlights

David MA’s listed patent connects his work with high-level synthesis, RISC-V processors, and FPGA-based hardware acceleration. The provided information associates him with Microsemi SOC Corporation.

Collaborations

The supplied information names Jongsok Choi and Ruolong Lian as David MA’s coworkers. It does not specify their roles in the patent or describe particular collaborative contributions.

Conclusion

David MA’s listed invention addresses the division of software and hardware tasks in RISC-V SoC generation, combining processor execution with reprogrammable hardware acceleration.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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