St. Charles, MO, United States of America

David Louis Vadnais

This inventor holds 3 USPTO granted patents. Top assignees: Memc Electronic Materials, Inc., Monsanto Company. Active years: 1976-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: David Louis Vadnais. Retrieved from https://idiyas.com/inventor/david-louis-vadnais

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 3

Forward Citations = 34(Granted Patents)


Company Filing History:


Years Active: 1976-2004

Loading Chart...
3 patents (USPTO):Explore Patents

Title: David Louis Vadnais: Innovator in Semiconductor Polishing Technology

Introduction

David Louis Vadnais is a notable inventor based in St. Charles, MO (US). He has made significant contributions to the field of semiconductor technology, particularly in the area of wafer polishing. With a total of 3 patents to his name, Vadnais has developed innovative solutions that enhance the efficiency and effectiveness of semiconductor manufacturing processes.

Latest Patents

Vadnais's latest patents include a polishing apparatus, polishing head, and method designed specifically for polishing semiconductor wafers. This wafer polishing apparatus features a base, a turntable, a polishing pad, and a head drive mechanism that enables the driven rotation of a polishing head. The polishing head is equipped with a sealing ring that holds at least one wafer, ensuring that the front surface of the wafer engages effectively with the work surface of the polishing pad. This design allows for the application of uniform air pressure over the rear surface of the wafer, with the sealing ring constructed to define a portion of a pressure cavity that receives pressurized air.

Another significant patent by Vadnais is the flattening process for epitaxial semiconductor wafers. This process prepares an epitaxial wafer with a total thickness variation and/or site total indicated reading of less than about 1.0 µm. The method involves measuring the distance between the front and back surfaces of the epitaxial wafer at discrete positions to generate thickness profile data. Additional stock is then removed from the front surface of the wafer to achieve the target thickness, taking into account the thickness profile data.

Career Highlights

Throughout his career, Vadnais has worked with prominent companies in the semiconductor industry, including Memc Electronic Materials, Inc. and Monsanto Company. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Vadnais has collaborated with several professionals in his field, including Ankur H Desai and Robert Wendell Standley. These collaborations have likely enriched his work and contributed to the development of his patented technologies.

Conclusion

David Louis Vadnais is a distinguished inventor whose work in semiconductor polishing technology has made a significant impact on the industry. His innovative patents and career achievements reflect his dedication to advancing semiconductor manufacturing processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…